As the rapid development of the semiconductor process, more and more electronic products can be provided with higher performance, higher portability and more compactness. Under such a development trend, the size of the chip used for the electronic products should be miniaturized, but the integrated circuits contained in the chip are becoming more and more complicated. However, advancing scaling down of chip size and increasing the design complexity of the integrated circuits entail a multiplicity of problems, such as, the crosstalk effect and the thermal issues on the chip, or the proximity effect in the lithography and etching processes. Recently, a novel three dimensional wafer structure design has been gradually developed in order to overcome the problems resulting from the miniaturization of the chip
Please refer to FIG. 1, which schematically shows a conventional three dimensional wafer stack structure according to the prior art. As can be seen from FIG. 1, a wafer stack 100′ includes a first wafer 10′, a second wafer 20′ and a third wafer 30′, each of which consists of a substrate 12′, 22′, 32′ and a device layer 14′, 24′, 34′. Furthermore, there further exits a bonding layer 13′ between two adjacent wafers for constructing the wafer stack. Specifically, the respective device layers of the first and the second wafers are arranged to configure them as a face to face wafer stack, while the respective device layers of the second and the third wafers are arranged to configure them as a back to face wafer stack. Furthermore, as can be seen from FIG. 1, each wafers 10′, 20′, 30′ further has plural circuit devices 16′, 26′, 36′ in the respective device layer 14′, 24′, 34′, which are electrically interconnected through the signal via 15′. Some low-k materials 18′, 28′ are disposed adjacent to those circuit devices 16′ and 26′ for the need of isolation.
In such a three dimensional wafer stack structure, like the abovementioned wafer stack 100′, more wafers might be repeatedly stacked up, if necessary. However, a new problem may occur in such a three dimensional wafer stack structure. The low-k materials 18′, 28′, which exist in the respective device layer and are used for allowing the conducting wires thereof being arranged closely, usually has porous structure, and might be destroyed by compression stresses resulting from the stacking structure or by the thermal stresses resulting from the heat generated by the circuit devices. Therefore, those low-k materials 18′, 28′ are vulnerable. Once the structure of the low-k material 18′ is damaged, the isolation between the circuit device 16′ and the other components in the same device layer 14′ would be no longer effective and the functions of the circuit device 16′ will eventually fail.
Based on the above, it is necessary to find a new approach to prevent the low-k materials 18′ existing in the device layer 14′ from being damaged by the compression or thermal stresses. In order to overcome such issues, a novel three dimensional wafer stack having therein at least one supporting pedestal and the manufacturing method therefor are provided. The supporting structure, such as a pedestal or a post, is disposed in a device layer, stands at an interface between the device layer and the substrate, and extends to the upper surface of the device layer, to protect the electronic devices in the same layer.